Chapter 12
318 MIPS R4000 Microprocessor User's Manual
12.5 Handling Requests
This section details the sequence, protocol, and syntax (See Terminology, in
this chapter, for definitions of these terms) of both processor and external
requests. The following system events are discussed:
• load miss in secondary-cache mode and no-secondary-cache
mode
• store miss in secondary-cache mode and no-secondary-cache
mode
• store hit
• uncached loads/stores
• CACHE operations
• load linked store conditional.
Load Miss
When a processor load misses in both the primary and secondary caches,
before the processor can proceed it must obtain the cache line that contains
the data element to be loaded from the external agent.
If the new cache line replaces a current dirty exclusive or dirty shared
cache line, the current cache line must be written back before the new line
can be loaded in the primary and secondary caches.
The processor examines the coherency attribute (cache coherency
attributes are described in Chapter 11) in the TLB entry for the page that
contains the requested cache line, and executes one of the following
requests:
• If the coherency attribute is exclusive, the processor issues a
coherent read request that also requests exclusivity.
• If the coherency attribute is sharable or update, the processor
issues a coherent read request.
• If the coherency attribute is noncoherent, the processor issues a
noncoherent read request.
Table 12-3 shows the actions taken on a load miss to primary and
secondary caches.
To Next Page
Loading...