Mips Technologies R4000 - Page 349

MIPS R4000 Microprocessor User's Manual 319
System Interface
Table 12-3 Load Miss to Primary and Secondary Caches
Page Attribute
(Write-back policy)
Processor
Configuration
State of Data Cache Line Being Replaced
No-Secondary-Cache
Mode
Secondary-Cache Mode
Clean/Invalid Dirty Clean/Invalid Dirty
Noncoherent
All R4000
models
NCR NCR/W NCR NCR-W
Exclusive
(read and write
invalidate)
R4000SC
R4000MC
N/A N/A R
Ex
R
Ex
-W
Shareable
(write invalidate)
R4000MC N/A N/A R R-W
Update
(write update)
R4000MC N/A N/A R R-W
NCR................... Processor noncoherent block read request
NCR/W............ Processor noncoherent block read request followed by processor block write
request
NCR-W ............. Cluster: Processor noncoherent block read request with write forthcoming
followed by processor block write request
R......................... Processor coherent block read request
R-W ................... Cluster: Processor coherent block read request with write forthcoming followed
by processor block write request
R
Ex
..................... Processor coherent block read request with exclusivity
R
Ex
-W................ Cluster: Processor coherent block read request with exclusivity and write
forthcoming followed by processor block write request