Mips Technologies R4000 - Initialization Sequence

Chapter 9
218 MIPS R4000 Microprocessor User's Manual
9.3 Initialization Sequence
The boot-mode initialization sequence begins immediately after VCCOk
is asserted. As the processor reads the serial stream of 256 bits through the
ModeIn pin, the boot-mode bits initialize all fundamental processor
modes (the signals used are described in Chapter 8).
The initialization sequence is listed below.
1. The system deasserts the VCCOk signal. The ModeClock output
is held asserted.
2. The processor synchronizes the ModeClock output at the time
VCCOk is asserted. The first rising edge of ModeClock occurs
256 MasterClock cycles after VCCOk is asserted.
3. Each bit of the initialization stream is presented at the ModeIn pin
after each rising edge of the ModeClock. The processor samples
256 initialization bits from the ModeIn input.
Figures 9-1, 9-2, and 9-3 on the next three pages show the timing diagrams
for the power-on, warm, and cold resets.