MIPS R4000 Microprocessor User's Manual 219
Figure 9-1 Power-on Reset
Power-on Reset (POR)
MasterClock
VCCOK
ModeClock
ModeIn
ColdReset*
Reset*
MasterOut
SyncOut
TClock
RClock
TDS
Undefined
Undefined
Vcc
TMDS
TDS
> 100ms
TDS
256 MClk cycles
5.25V
4.75V
TDS
Bit 0
TMDH
> 64K MClk cycles*
> 64 MClk cycles
Bit
TDS
Bit 1
256
cycles
MClk
Reset*
(MClk)
255
Undefined
Undefined
TClock and RClock are stable
after 64 MClk cycles
*Considering multiple processing variables and systems-
related variables that cannot be duplicated on the tester, a larger
number greater than or equal to 100 ms is recommended
For all div. modes, assume the rising edges are
synchronized to this edge of MasterClock.
Wavy lines indicate one or more identical
cycles, not shown due to space constraints
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