Mips Technologies R4000 - Integer Overflow Exception

MIPS R4000 Microprocessor User's Manual 135
CPU Exception Processing
the physical page number. The process executing at the time of this
exception is handed a UNIX SIGBUS (bus error) signal, which is usually
fatal.
Integer Overflow Exception
Cause
An Integer Overflow exception occurs when an ADD, ADDI, SUB, DADD,
DADDI or DSUB
†
instruction results in a 2’s complement overflow. This
exception is not maskable.
Processing
The common exception vector is used for this exception, and the OV code
in the Cause register is set.
The EPC register contains the address of the instruction that caused the
exception unless the instruction is in a branch delay slot, in which case the
EPC register contains the address of the preceding branch instruction and
the BD bit of the Cause register is set.
Integer Overflow exception processing is shown in Figure 5-17.
Servicing
The process executing at the time of the exception is handed a UNIX
SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer
overflow) signal. This error is usually fatal to the current process.
† See Appendix A for a description of these instructions.