Chapter 14
396 MIPS R4000 Microprocessor User's Manual
TAP Controller
The processor implements the 16-state TAP controller as defined in the
IEEE JTAG specification.
Controller Reset
The TAP controller state machine can be put into Reset state by one of the
following:
• deassertion of the VCCOk input resets the TAP controller
• keeping the JTMS input signal asserted through five
consecutive rising edges of JTCK input sends the TAP
controller state machine into its Reset state.
In either case, keeping JTMS asserted maintains the Reset state.
Controller States
The TAP controller has four states: Reset, Capture, Shift, and Update.
They can reflect either instructions (as in the Shift-IR state) or data (as in
the Capture-DR state).
• When the TAP controller is in the Reset state, the value 0x7 is
loaded into the parallel output latch, selecting the Bypass
register as default. The three most significant bits of the
Boundary-scan register are cleared to 0, disabling the outputs.
• When the TAP controller is in the Capture-IR state, the value
0x4 is loaded into the shift register stage.
• When the TAP controller is in the Capture-DR (Boundary-scan)
state, the data currently on the processor input and I/O pins is
latched into the Boundary-scan register. In this state, the
Boundary-scan register bits corresponding to output pins are
arbitrary and cannot be checked during the scan out process.
• When the TAP controller is in the Shift-IR state, data is loaded
serially into the shift register stage of the Instruction register
from the JTDI input pin, and the MSB of the Instruction
register’s shift register stage is shifted onto the JTDO pin.
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