Mips Technologies R4000 - Secondary Cache Transfers

MIPS R4000 Microprocessor User's Manual 357
System Interface
In Tables 12-6 and 12-7, data patterns are specified using the letters D and
x; D indicates a data cycle and x indicates an unused cycle. Figure 12-40
shows a read response in which data is provided to the processor at a rate
of two doublewords every three cycles using the data pattern DDx.
Figure 12-40 Read Response, Reduced Data Rate, System Interface in Slave State
Secondary Cache Transfers
The processor operates most efficiently if data is delivered in pairs of
doublewords, since the secondary cache is organized as a 128-bit RAM
array. The most efficient way of reducing the data rate is to deliver a pair
of doublewords followed by some number of unused cycles, followed by
another pair of doublewords. The secondary cache write cycle time
should determine the rate at which this pattern is repeated. However, the
processor accepts data in any pattern as long as the time between the
transfer of any pair of odd-numbered doublewords is greater than, or
equal to, the write cycle time of the secondary cache. Doublewords in the
transfer pattern are numbered beginning at 0: the odd-numbered
doublewords are the second, fourth, sixth, and so on.
SCycle
1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
Data0 Data1 Data2 Data3
SysCmd Bus
CData CData CData CEOD
ValidOut*
ValidIn*
ExtRqst*
Release*