MIPS R4000 Microprocessor User's Manual 101
CPU Exception Processing
5.2 Exception Processing Registers
This section describes the CP0 registers that are used in exception
processing. Table 5-1 lists these registers, along with their number—each
register has a unique identification number that is referred to as its register
number. For instance, the ECC register is register number 26. The
remaining CP0 registers are used in memory management, as described in
Chapter 4.
Software examines the CP0 registers during exception processing to
determine the cause of the exception and the state of the CPU at the time
the exception occurred. The registers in Table 5-1 are used in exception
processing, and are described in the sections that follow.
Table 5-1 CP0 Exception Processing Registers
CPU general registers are interlocked and the result of an instruction can
normally be used by the next instruction; if the result is not available right
away, the processor stalls until it is available. CP0 registers and the TLB
are not interlocked, however; there may be some delay before a value
written by one instruction is available to following instructions. For more
information please see Appendix F.
Register Name Reg. No.
Context 4
BadVAddr (Bad Virtual Address) 8
Count 9
Compare register 11
Status 12
Cause 13
EPC (Exception Program Counter) 14
WatchLo (Memory Reference Trap Address Low) 18
WatchHi (Memory Reference Trap Address High) 19
XContext 20
ECC 26
CacheErr (Cache Error and Status) 27
ErrorEPC (Error Exception Program Counter) 30
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