Mips Technologies R4000 - Cache State Transition Diagrams

Chapter 11
260 MIPS R4000 Microprocessor User's Manual
11.7 Cache State Transition Diagrams
The following sections describe the cache state diagrams that illustrate the
cache state transitions for both the primary and secondary caches. Figures
11-9 and 11-10 are state diagrams of the primary and secondary caches,
respectively.
When an external agent supplies a cache line, the initial state of the cache
line is specified by the external agent (see Chapter 12 for a definition of an
external agent). Otherwise, the processor changes the state of the cache
line during one of the following events:
• A store to a clean exclusive cache line causes the state to be
changed to dirty exclusive in both the primary and secondary
caches.
• A store to a shared cache line—that is a line marked shared in
the primary cache and either shared or dirty shared in the
secondary cache—causes the processor to issue either an
invalidate request or an update request (depending on the
coherency attribute in the TLB entry for the page containing
the cache line). And update page attribute causes an update
request to be issued; a sharable page attribute causes an
invalidate request to be issued.
- Upon successful completion of an invalidate, the
processor completes the store and changes the state of the
cache line to dirty exclusive in both the primary and
secondary caches.
- Upon successful completion of an update, the processor
completes the store and changes the state of the cache line
to shared in the primary cache and dirty shared in the
secondary cache if dirty shared mode is enabled. Dirty
shared mode is programmable through the boot-time
mode control interface (see Chapter 9 for a description of
boot mode bits). If dirty shared mode is not enabled, the
state of the primary and secondary caches are left in a
shared state, after successful completion of an update.
• A store to a dirty exclusive line remains in a dirty exclusive
state.
These state diagrams do not cover the initial state of the system since the
initial state is system dependent.