Mips Technologies R4000 - 8-Word Read Cycle; Notes on a Secondary Cache Read Cycle

Chapter 13
384 MIPS R4000 Microprocessor User's Manual
8-Word Read Cycle
The 8-word read cycle has an additional user-accessible parameter beyond
that of the 4-word read cycle described above: t
Rd2Cyc
, the time from the
first sample point to the second sample point.
In an 8-word read cycle, the low-order address bit, SCAddr(0), changes at
the same time as the first read sample point.
Figure 13-3 illustrates the 8-word read cycle, including the three user-
accessible timing parameters.
Figure 13-3 Timing Diagram of an 8-Word Read Cycle
Notes on a Secondary Cache Read Cycle
All read cycles can be aborted by changing the address; a new cycle begins
with the edge on which the address is changed. Additionally, the period
t
Dis
after a read cycle can be interrupted any time by the start of a new
read cycle. If a read cycle is aborted by a write cycle, SCOE* must be
deasserted for the t
Dis
period before the write cycle can begin.
Read cycles can also be extended indefinitely. There is no requirement to
change the address at the end of a read cycle.
PCycle
1 2 3 4 5 6 7 8 9
SCAddr(17:1)
Address
t
Rd1Cyc
SCAddr(0)
First_Address Second_Address
t
Rd2Cyc
Data Data
SCOE*
t
Dis
SCDCS*
SCTCS*
SCData(127:0)
SCDChk(15:0)
SCAPar(2:0)
SCTag(24:0)
SCTChk(6:0)