Mips Technologies R4000 - CPU Pipeline Stages

MIPS R4000 Microprocessor User's Manual 45
The CPU Pipeline
3.2 CPU Pipeline Stages
This section describes each of the eight pipeline stages:
• IF - Instruction Fetch, First Half
• IS - Instruction Fetch, Second Half
• RF - Register Fetch
• EX - Execution
• DF - Data Fetch, First Half
• DS - Data Fetch, Second Half
• TC - Tag Check
• WB - Write Back
IF - Instruction Fetch, First Half
During the IF stage, the following occurs:
• Branch logic selects an instruction address and the instruction
cache fetch begins.
• The instruction translation lookaside buffer (ITLB) begins the
virtual-to-physical address translation.
IS - Instruction Fetch, Second Half
During the IS stage, the instruction cache fetch and the virtual-to-physical
address translation are completed.
RF - Register Fetch
During the RF stage, the following occurs:
• The instruction decoder (IDEC) decodes the instruction and
checks for interlock conditions.
• The instruction cache tag is checked against the page frame
number obtained from the ITLB.
• Any required operands are fetched from the register file.