Mips Technologies R4000 - Output Buffer ∆I;∆T Control Mechanism; Mode Bits

MIPS R4000 Microprocessor User's Manual 107
CPU Exception Processing
Table 5-3 (cont.) Status Register Fields
Field Description
UX
Enables 64-bit addressing and operations in User mode.
The extended-addressing TLB refill exception is used for
TLB misses on user addresses.
0 → 32−bit
1 → 64−bit
KSU
Mode bits
10
2
→ User
01
2
→ Supervisor
00
2
→ Kernel
ERL
Error Level; set by the processor when Reset, Soft Reset,
NMI, or Cache Error exception are taken.
0 → normal
1 → error
EXL
Exception Level; set by the processor when any exception
other than Reset, Soft Reset, NMI, or Cache Error exception
are taken.
0 → normal
1 → exception
IE
Interrupt Enable
0 → disable interrupts
1 → enables interrupts