Chapter 5
108 MIPS R4000 Microprocessor User's Manual
Figure 5-6 Status Register DS Field
Table 5-4 Status Register Diagnostic Status Bits
Bit Description
BEV
Controls the location of TLB refill and general exception
vectors.
0 → normal
1→ bootstrap
TS 1→ Indicates TLB shutdown has occurred (read-only).
SR
1→ Indicates a Reset* signal or NMI has caused a Soft Reset
exception
CH
Hit (tag match and valid state) or miss indication for last
CACHE Hit Invalidate, Hit Write Back Invalidate, Hit Write
Back, Hit Set Virtual, or Create Dirty Exclusive for a
secondary cache.
0 → miss
1 → hit
CE
Contents of the ECC register set or modify the check bits of the
caches when CE = 1; see description of the ECC register.
DE
Specifies that cache parity or ECC errors cannot cause
exceptions.
0 → parity/ECC remain enabled
1 → disables parity/ECC
0
Reserved. Must be written as zeroes, and returns zeroes
when read.
Diagnostic Status Field
24 22 21 20 19 18 17 16
TS SR CH CE DE
2111111
BEV
23
1
00
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