MIPS R4000 Microprocessor User's Manual 11
Introduction
Superpipeline Architecture
The R4000 processor exploits instruction parallelism by using an eight-
stage superpipeline which places no restrictions on the instruction issued.
Under normal circumstances, two instructions are issued each cycle.
The internal pipeline of the R4000 processor operates at twice the
frequency of the master clock, as discussed in Chapter 3. The processor
achieves high throughput by pipelining cache accesses, shortening
register access times, implementing virtual-indexed primary caches, and
allowing the latency of functional units to span more than one pipeline
clock cycles.
System Interface
The R4000 processor supports a 64-bit System interface that can construct
uniprocessor systems with a direct DRAM interface—with or without a
secondary cache—or cache-coherent multiprocessor systems. The System
interface includes:
• a 64-bit multiplexed address and data bus
• 8 check bits
• a 9-bit parity-protected command bus
• 8 handshake signals
The interface is capable of transferring data between the processor and
memory at a peak rate of 400 Mbytes/second, when running at 50 MHz.
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