MIPS R4000 Microprocessor User's Manual 159
Floating-Point Unit
Control/Status Register (FCR31)
The Control/Status register (FCR31) contains control and status
information that can be accessed by instructions in either Kernel or User
mode. FCR31 also controls the arithmetic rounding mode and enables
User mode traps, as well as identifying any exceptions that may have
occurred in the most recently executed instruction, along with any
exceptions that may have occurred without being trapped.
Figure 6-4 shows the format of the Control/Status register, and Table 6-3
describes the Control/Status register fields. Figure 6-5 shows the Control/
Status register Cause, Flag, and Enable fields.
Figure 6-4 FP Control/Status Register Bit Assignments
Table 6-3 Control/Status Register Fields
Field Description
FS
When set, denormalized results are flushed to 0 instead of causing an
unimplemented operation exception.
C Condition bit. See description of Control/Status register Condition bit.
Cause
Cause bits. See Figure 6-5 and the description of Control/Status register
Cause, Flag, and Enable bits.
Enables
Enable bits. See Figure 6-5 and the description of Control/Status register
Cause, Flag, and Enable bits.
Flags
Flag bits. See Figure 6-5 and the description of Control/Status register
Cause, Flag, and Enable bits.
RM
Rounding mode bits. See Table 6-4 and the description of Control/Status
register Rounding Mode Control bits.
Control/Status Register (FCR31)
31 24 23 22 18 17 12 11 7 6 2 1 0
7156552
C
RM
FlagsEnablesCause
0 0
E V Z O U I V Z O U I V Z O U I
25
FS
1
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