MIPS R4000 Microprocessor User's Manual 27
Introduction
Coprocessors (CP0-CP2)
The MIPS ISA defines three coprocessors (designated CP0 through CP2):
• Coprocessor 0 (CP0) is incorporated on the CPU chip and
supports the virtual memory system and exception handling.
CP0 is also referred to as the System Control Coprocessor.
• Coprocessor 1 (CP1) is reserved for the on-chip, floating-point
coprocessor, the FPU.
• Coprocessor 2 (CP2) is reserved for future definition by MIPS.
CP0 and CP1 are described in the sections that follow.
System Control Coprocessor, CP0
CP0 translates virtual addresses into physical addresses and manages
exceptions and transitions between kernel, supervisor, and user states.
CP0 also controls the cache subsystem, as well as providing diagnostic
control and error recovery facilities.
The CP0 registers shown in Figure 1-10 and described in Table 1-19
manipulate the memory management and exception handling capabilities
of the CPU.
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