Chapter 1
26 MIPS R4000 Microprocessor User's Manual
The CPU uses byte addressing for halfword, word, and doubleword
accesses with the following alignment constraints:
• Halfword accesses must be aligned on an even byte boundary
(0, 2, 4...).
• Word accesses must be aligned on a byte boundary divisible by
four (0, 4, 8...).
• Doubleword accesses must be aligned on a byte boundary
divisible by eight (0, 8, 16...).
The following special instructions load and store words that are not
aligned on 4-byte (word) or 8-word (doubleword) boundaries:
LWL LWR SWL SWR
LDL LDR SDL SDR
These instructions are used in pairs to provide addressing of misaligned
words. Addressing misaligned data incurs one additional instruction
cycle over that required for addressing aligned data.
Figures 1-8 and 1-9 show the access of a misaligned word that has byte
address 3.
Figure 1-8 Big-Endian Misaligned Word Addressing
Figure 1-9 Little-Endian Misaligned Word Addressing
Higher
Address
Lower
Address
Bit #
45 6
3
31 24 23 16 15 8 7 0
Higher
Address
Lower
Address
31 24 23 16 15 8 7 0
Bit #
3
645
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