MIPS R4000 Microprocessor User's Manual 153
Floating-Point Unit
6.2 FPU Features
This section briefly describes the operating model, the load/store
instruction set, and the coprocessor interface in the FPU. A more detailed
description is given in the sections that follow.
• Full 64-bit Operation. When the FR bit in the CPU Status
register equals 0, the FPU is in 32-bit mode and contains thirty-
two 32-bit registers that hold single- or, when used in pairs,
double-precision values. When the FR bit in the CPU Status
register equals 1, the FPU is in 64-bit mode and the registers
are expanded to 64 bits wide. Each register can hold single- or
double-precision values. The FPU also includes a 32-bit Control/
Status register that provides access to all IEEE-Standard
exception handling capabilities.
• Load and Store Instruction Set. Like the CPU, the FPU uses a
load- and store-oriented instruction set, with single-cycle load
and store operations. Floating-point operations are started in a
single cycle and their execution overlaps other fixed-point or
floating-point operations.
• Tightly Coupled Coprocessor Interface. The FPU resides on-
chip to form a tightly coupled unit with a seamless integration
of floating-point and fixed-point instruction sets. Since each
unit receives and executes instructions in parallel, some
floating-point instructions can execute at the same single-cycle-
per-instruction rate as fixed-point instructions.
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