Mips Technologies R4000 - R4000 Cache Description

Chapter 9
216 MIPS R4000 Microprocessor User's Manual
Power-on Reset
The sequence for a power-on reset is listed below.
1. Power-on reset applies a stable Vcc of at least 4.75 volts from the
+5 volt power supply to the processor. It also supplies a stable,
continuous system clock at the processor operational frequency.
2. After at least 100 ms of stable Vcc and MasterClock, the VCCOk
signal is asserted to the processor. The assertion of VCCOk
initializes the processor operating parameters. After the mode
bits have been read in, the processor allows its internal phase
locked loops to lock, stabilizing the processor internal clock,
PClock, the SyncOut-SyncIn clock path (described in Chapter
10), and the master clock output, MasterOut. Note that when
JTAG is not used, JTCK must be tied low at the rising edge of
VCCOk for the processor to properly reset. If JTAG is used, JTCK
may be toggled during power-up.
3. ColdReset* is asserted for at least 64K (2
16
) MasterClock cycles
after the assertion of VCCOk. Once the processor reads the boot-
time mode control serial data stream, ColdReset* can be
deasserted. ColdReset* must be deasserted synchronously with
MasterClock.
4. The deassertion of ColdReset* synchronizes the rising edges of
SClock and TClock with the rising edge of the next MasterClock,
aligning SClock, TClock, and RClock (which is 90 degrees ahead
of phase with SClock and TClock) of all processors in a
multiprocessor system. However, these clocks are only
guaranteed to be stabilized 64 MasterClock cycles after
ColdReset* is deasserted.
5. After ColdReset* is deasserted synchronously and SClock,
TClock, and RClock have stabilized, Reset* is deasserted to allow
the processor to begin running. (Reset* must be held asserted for
at least 64 MasterClock cycles after the deassertion of
ColdReset*.) Reset* must be deasserted synchronously with
MasterClock.
NOTE: ColdReset* must be asserted when VCCOk asserts. The
behavior of the processor is undefined if VCCOk asserts while
ColdReset* is deasserted.