Chapter 12
354 MIPS R4000 Microprocessor User's Manual
Read Response Protocol
An external agent must return data to the processor in response to a
processor read request by using a read response protocol. A read response
protocol consists of the following steps:
1. The external agent waits for the processor to perform an uncompelled
change to slave state.
2. The processor returns the data through a single data cycle or a series
of data cycles.
3. After the last data cycle is issued, the read response is complete and
the external agent sets the SysCmd and SysAD buses to a tri-state.
4. The System interface returns to master state.
NOTE: The processor always performs an uncompelled change to
slave state after issuing a read request.
5. The data identifier for data cycles must indicate the fact that this data
is response data.
6. The data identifier associated with the last data cycle must contain a
last data cycle indication.
For read responses to coherent block read requests, each data identifier
must include the cache state of the response data. The cache state
provided with each data identifier must be the same and must be clean
exclusive, dirty exclusive, shared, or dirty shared. The behavior of the
processor is undefined if the cache state provided with the data identifiers
changes during the transfer of the block of data, or if the cache state
provided is invalid.
The data identifier associated with a data cycle can indicate that the data
transmitted during that cycle is erroneous; however, an external agent
must return a data block of the correct size regardless of the fact that the
data may be in error. If a read response includes one or more erroneous
data cycles, the processor then takes a bus error.
Read response data must only be delivered to the processor when a
processor read request is pending. The behavior of the processor is
undefined when a read response is presented to it and there is no
processor read pending. Further, if the processor issues a read-with-write-
forthcoming request, a processor write request or a processor null write
request must be accepted before the read response can be returned. The
behavior of the processor is undefined if the read response is returned
before a processor write request is accepted.
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