Mips Technologies R4000 - Entrylo0 (2), and Entrylo1 (3) Registers; Pagemask Register (5)

MIPS R4000 Microprocessor User's Manual 87
Memory Management
EntryLo0 (2), and EntryLo1 (3) Registers
The EntryLo register consists of two registers that have identical formats:
• EntryLo0 is used for even virtual pages.
• EntryLo1 is used for odd virtual pages.
The EntryLo0 and EntryLo1 registers are read/write registers. They hold
the physical page frame number (PFN) of the TLB entry for even and odd
pages, respectively, when performing TLB read and write operations.
Figure 4-10 shows the format of these registers.
PageMask Register (5)
The PageMask register is a read/write register used for reading from or
writing to the TLB; it holds a comparison mask that sets the variable page
size for each TLB entry, as shown in Table 4-9.
TLB read and write operations use this register as either a source or a
destination; when virtual addresses are presented for translation into
physical address, the corresponding bits in the TLB identify which virtual
address bits among bits 24:13 are used in the comparison. When the Mask
field is not one of the values shown in Table 4-9, the operation of the TLB
is undefined.
Table 4-9 Mask Field Values for Page Sizes
Page Size
Bit
24 23 22 21 20 19 18 17 16 15 14 13
4 Kbytes 0 0 0 0 0 0 0 0 0 0 0 0
16 Kbytes 0 0 0 0 0 0 0 0 0 011
64 Kbytes 0 0 0 0 0 0 0 01111
256 Kbytes 0 0 0 0 0 0111111
1 Mbyte 0 0 0 011111111
4 Mbytes 0 01111111111
16 Mbytes 111111111111