MIPS R4000 Microprocessor User's Manual 255
Cache Organization, Operation, and Coherency
11.4 Cache States
The four terms below are used to describe the state of a cache line:
• Exclusive: a cache line that is present in exactly one cache in
the system is exclusive, and may be in one of the exclusive
states.
• Dirty: a cache line that contains data that has changed since it
was loaded from memory is dirty, and must be in one of the
dirty or shared states.
• Clean: a cache line that contains data that has not changed
since it was loaded from memory is clean, and may be in one
of the clean states.
• Shared: a cache line that is present in more than one cache in
the system.
Each primary and secondary cache line in the R4000 system is in one of the
states described in Table 11-3. Table 11-3 also lists with the types of cache
and the R4000 models in which the various states may be found.
Table 11-3 Cache States
Cache
Line
State
Description
Where the
State is
Used
Available on
the Following
R4000 Models
Invalid
A cache line that does not contain valid
information must be marked invalid, and
cannot be used. For example, a cache line is
marked invalid if the same information,
located in another cache, is modified. A cache
line in any other state than invalid is assumed
to contain valid information.
Primary or
Secondary
Cache
R4000PC
R4000SC
R4000MC
Shared
A cache line that is present in more than one
cache in the system is shared.
Primary or
Secondary
Cache
R4000MC
only
Dirty
Shared
A dirty shared cache line contains valid
information and can be present in another
cache. This cache line is inconsistent with
memory and is owned by the processor (see the
section titled Cache Line Ownership in this
chapter).
Secondary
cache only
R4000MC
only
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