Mips Technologies R4000 - Processor Invalidate or Update Requests

MIPS R4000 Microprocessor User's Manual 273
Cache Organization, Operation, and Coherency
Processor Invalidate or Update Requests
For processor invalidate or compulsory update requests, a cancellation
mechanism indicates a conflict. For example, if an external coherency
request is submitted while a processor invalidate or compulsory update
request has been issued but not yet acknowledged, the conflict is resolved
when the external agent cancels the processor invalidate or compulsory
update.
Cancellation is accomplished by setting the cancellation bit in the
command for the coherency request [SysCmd(4)]. The processor, upon
receiving an external coherency request with the cancellation bit set,
considers its invalidate or update request to be acknowledged and
cancelled. The processor again accesses the secondary cache to determine
whether to reissue the invalidate or update request, or to issue a read
request.
An external agent can only assert the cancellation bit during an
unacknowledged processor invalidate or unacknowledged compulsory
update request. If an external coherency request is issued with the
cancellation bit set, and there is no unacknowledged processor invalidate
or update request pending, the behavior of the processor is undefined.
If an external coherency request is issued with the cancellation bit set
when a processor update request remains potential—in other words,
while a processor read request is currently pending—the behavior of the
processor is undefined.
Processor potential update requests cannot be cancelled. Potential
updates are always issued with processor read requests and become
compulsory only after the response to the processor read request is
returned in one of the shared states.