Mips Technologies R4000 - Instruction Execution Cycle Time

MIPS R4000 Microprocessor User's Manual 173
Floating-Point Unit
Figure 6-10 FPU Pipeline Stall
To lessen the performance impact that results from stalling the instruction
pipeline, the FPU allows instructions to overlap so that instruction
execution can proceed as long as there are no resource conflicts, data
dependencies, or exception conditions. The following sections describe
the timing and overlapping of FPU instructions.
Instruction Execution Cycle Time
Unlike the CPU, which executes almost all instructions in a single cycle,
more time may be required to execute FPU instructions.
Table 6-14 gives the minimum latency, in processor pipeline cycles, of each
floating-point operation for the currently implemented configurations.
These latency calculations assume the result of the operation is
immediately used in a succeeding operation.
IF IS RF EX DF
IF IS
RF EX
DS
IF IS
RF
DF DS
IF IS
stall EX DF
DS
IF
RF EX DF
DS
stall stall
DF
EX
RF
IS
WB
TC
DS
TC WB
WB
TC
TC
WB
WB
TC
stall stall stall
stall stall stall
stall stall stall
stall stall stall