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Mips Technologies R4000 - Clusters

Mips Technologies R4000
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MIPS R4000 Microprocessor User's Manual 311
System Interface
Clusters
A cluster consists of a single processor read request, followed by one or
two additional processor requests that are issued while the initial read
request is pending.
The processor supports three types of clusters:
a processor read request, followed by a write request
a processor read request, followed by potential update request
a processor read request, followed by a potential update
request, followed by a write request.
In secondary-cache mode, the processor issues individual requests (as in
no-secondary-cache mode), or cluster requests. All requests in the cluster
must be accepted before the response to the read request that began the
cluster can be returned to the processor.
Potential update requests within a cluster can be disabled through the
boot-time mode control interface.
Read With Write Forthcoming Request as Part of a Cluster
The processor signals that it is issuing a cluster containing a processor
write request by issuing a read-with-write-forthcoming request, instead of
starting the cluster with an ordinary read request. The read-with-write-
forthcoming request is identified by a bit in the command for processor
read requests.
The external agent must accept all requests that form the cluster before it
can respond to the read request that began the cluster. The behavior of the
processor is undefined if the external agent returns a response to a
processor read request before accepting all of the requests of the cluster.
Potential Update as Part of a Cluster
Potential updates are identified by setting a bit in the processor update
command. A processor potential update request is any update request
that is issued while a processor read request is pending.
Once the processor issues a read request, a potential update request
follows, regardless of the state of RdRdy*. Potential update requests do
not obey the RdRdy* flow control rules for issuance, but rather issue with
a single address cycle regardless of the state of RdRdy*.

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