Mips Technologies R4000 - TLB Modified Exception

MIPS R4000 Microprocessor User's Manual 131
CPU Exception Processing
TLB Modified Exception
Cause
The TLB modified exception occurs when a store operation virtual address
reference to memory matches a TLB entry that is marked valid but is not
dirty and therefore is not writable. This exception is not maskable.
Processing
The common exception vector is used for this exception, and the Mod code
in the Cause register is set.
When this exception occurs, the BadVAddr, Context, XContext and EntryHi
registers contain the virtual address that failed address translation. The
EntryHi register also contains the ASID from which the translation fault
occurred. The contents of the EntryLo register are undefined.
The EPC register contains the address of the instruction that caused the
exception unless that instruction is in a branch delay slot, in which case the
EPC register contains the address of the preceding branch instruction and
the BD bit of the Cause register is set.
TLB Modified exception processing is shown in Figure 5-17.
Servicing
The kernel uses the failed virtual address or virtual page number to
identify the corresponding access control information. The page
identified may or may not permit write accesses; if writes are not
permitted, a write protection violation occurs.
If write accesses are permitted, the page frame is marked dirty/writable
by the kernel in its own data structures. The TLBP instruction places the
index of the TLB entry that must be altered into the Index register. The
EntryLo register is loaded with a word containing the physical page frame
and access control bits (with the D bit set), and the EntryHi and EntryLo
registers are written into the TLB.