Mips Technologies R4000 - Exception Program Counter (EPC) Register (14)

Chapter 5
112 MIPS R4000 Microprocessor User's Manual
Exception Program Counter (EPC) Register (14)
The Exception Program Counter (EPC) is a read/write register that
contains the address at which processing resumes after an exception has
been serviced.
For synchronous exceptions, the EPC register contains either:
• the virtual address of the instruction that was the direct cause
of the exception, or
• the virtual address of the immediately preceding branch or
jump instruction (when the instruction is in a branch delay
slot, and the Branch Delay bit in the Cause register is set).
The processor does not write to the EPC register when the EXL bit in the
Status register is set to a 1.
Figure 5-8 shows the format of the EPC register.
Figure 5-8 EPC Register Format
EPC Register
31
0
EPC
32
63
0
EPC
64
32-bit
Mode
64-bit
Mode