Mips Technologies R4000 - Read Cycles; 4-Word Read Cycle

MIPS R4000 Microprocessor User's Manual 383
Secondary Cache Interface
Read Cycles
There are two basic read cycles: 4-word read and 8-word read.
Each secondary cache read cycle begins by driving an address out on the
address pins. The output enable signal SCOE* is asserted at the same
time.
This section describes both 4-word and 8-word read cycles, including
timing diagrams.
4-Word Read Cycle
The 4-word read cycle has two user-accessible timing parameters:
t
Rd1Cyc
read sequence cycle time, which specifies the
time from the assertion of the SCAddr bus to
the sampling of the SCData bus
t
Dis
cache output disable time, which specifies the
time from the end of a read cycle to the start of
the next write cycle
Figure 13-2 illustrates the 4-word read cycle, including the two user-
accessible timing parameters.
Figure 13-2 Timing Diagram of a 4-Word Read Cycle
PCycle
1 2 3 4 5 6
SCAddr(17:0)
Address
t
Rd1Cyc
Data
SCOE*
t
Dis
SCDCS*:
SCTCS*:
SCAPar(2:0)
SCData(127:0)
SCDChk(15:0)
SCTag(24:0)
SCTChk(6:0)