Chapter 16
436 MIPS R4000 Microprocessor User's Manual
Reset Operation
When the R4400 processor is a Complete Listener, SIMaster, or SCMaster,
an assertion of Reset* after the initial boot sequence is significant.
If Reset* is asserted a second time and subsequently deasserted, the R4400
processor changes to Forced Complete Master mode and drives all
outputs.
If Reset* is asserted and deasserted a third time, the R4400 processor
returns to its prior mode, as programmed by the boot-mode bits.
On any subsequent assertion and deassertion of Reset*, the processor
alternates between the two modes described above: the mode determined
by boot-time mode bits if the Master/Checker mode is Complete Listener,
SIMaster, or SCMaster, or Forced Complete Master mode.
In Forced Complete Master mode, the Fault* pin reports all output faults,
not just faults of the System interface as are reported in Complete Master
mode.
Fault History
Two internal fault history bits, Output Fault History and Input Fault
History, record output faults and certain input faults reported through the
Fault* pin. These bits are cleared with each deassertion of Reset*.
The two fault history bits are readable when Reset* is asserted, and the
Fault* pin changes from reporting live faults to indicating which fault
history bit was set when Reset* was deasserted in the previous cycle. The
ModeIn pin acts as selector; if ModeIn = 0, Fault* indicates the inverted
state of the Output fault history bit. If ModeIn = 1, Fault* indicates the
inverted state of the Input fault history bit.
The fault history bits can be reset (cleared) while the R4400 processor is
running by asserting 1 to the ModeIn pin. Consequently, ModeIn must
be held to 0 to maintain the status of the fault history bits. Table 16-6
presents this information in tabular form.
To Next Page
Loading...