MIPS R4000 Microprocessor User's Manual 31
Introduction
Memory Management System (MMU)
The R4000 processor has a 36-bit physical addressing range of 64 Gbytes.
However, since it is rare for systems to implement a physical memory
space this large, the CPU provides a logical expansion of memory space by
translating addresses composed in the large virtual address space into
available physical memory addresses. The R4000 processor supports the
following two addressing modes:
• 32-bit mode, in which the virtual address space is divided into
2 Gbytes per user process and 2 Gbytes for the kernel.
• 64-bit mode, in which the virtual address is expanded to
1 Tbyte (2
40
bytes) of user virtual address space.
A detailed description of these address spaces is given in Chapter 4.
The Translation Lookaside Buffer (TLB)
Virtual memory mapping is assisted by a translation lookaside buffer,
which caches virtual-to-physical address translations. This fully-
associative, on-chip TLB contains 48 entries, each of which maps a pair of
variable-sized pages ranging from 4 Kbytes to 16 Mbytes, in multiples of
four.
Instruction TLB
The R4000 processor has a two-entry instruction TLB (ITLB) which assists
in instruction address translation. The ITLB is completely invisible to
software and exists only to increase performance.
Joint TLB
An address translation value is tagged with the most-significant bits of its
virtual address (the number of these bits depends upon the size of the
page) and a per-process identifier. If there is no matching entry in the TLB,
an exception is taken and software refills the on-chip TLB from a page
table resident in memory; this TLB is referred to as the joint TLB (JTLB)
because it contains both data and instructions jointly. The JTLB entry to
be rewritten is selected at random.
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