Mips Technologies R4000 - Cache Error Exception Process; Reset Exception Process

Chapter 5
120 MIPS R4000 Microprocessor User's Manual
Reset Exception Process
Figure 5-14 shows the Reset exception process.
Figure 5-14 Reset Exception Processing
Cache Error Exception Process
Figure 5-15 shows the Cache Error exception process.
Figure 5-15 Cache Error Exception Processing
T: undefined
Random ← TLBENTRIES–1
Wired ← 0
Config ← CM || EC || EP || SB || SS || SW || EW || SC || SM || BE || EM || EB || 0 || IC
|| DC || undefined
6
ErrorEPC ← RestartPC /* If the instruction is in a branch delay slot, RestartPC */
/* holds the value of PC-4, otherwise RestartPC = PC */
If R4400 then
CacheErr ← undefined
8
|| 0 || undefined
23
/* Set EW bit to 0 */
endif
SR ← SR
31:23
|| 1 || 0 || 0 || SR
19:3
|| 1 || SR
1:0
PC ← 0xFFFF FFFF BFC0 0000
T: ErrorEPC ← RestartPC /* If the instruction is in a branch delay slot, RestartPC */
/* holds the value of PC-4, otherwise RestartPC = PC */
if R4000 then
CacheErr ← ER || EC || ED || ET || ES || EE || EB || EI || 0
2
|| SIdx || PIdx
else /* R4400 */
CacheErr ← ER || EC || ED || ET || ES || EE || EB || EI || EW || 0 || SIdx || PIdx
endif
SR ← SR
31:3
|| 1 ||SR
1:0
if SR
22
= 1 then
PC ← 0xFFFF FFFF BFC0 0200 + 0x100
else
PC ← 0xFFFF FFFF A000 0000 + 0x100
endif