MIPS R4000 Microprocessor User's Manual 133
CPU Exception Processing
Virtual Coherency Exception
Cause
A Virtual Coherency exception occurs when all of the following conditions
are true:
• a primary cache miss hits in the secondary cache
• bits 14:12 of the virtual address were not equal to the
corresponding bits of the PIdx field of the secondary cache tag
• the cache algorithm for the page (from the C field in the TLB)
specifies that the page is cached
This exception is not maskable.
Processing
The common exception vector is used for this exception.
The VCEI or VCED code in the Cause register is set for instruction and data
cache misses respectively.
The BadVAddr register holds the virtual address that caused the exception.
Virtual Coherency exception processing is shown in Figure 5-17.
Servicing
Using the appropriate CACHE instruction(s), the primary cache line at
both the previous and the new virtual index should be invalidated
†
(and
written back, if necessary), and the PIDx field of the secondary cache
should be written with the new virtual index. Once completed, the
program continues.
Software can avoid the cost of this exception by using consistent virtual
primary cache indexes to access the same physical data.
† When a cache miss occurs, the processor refills the primary cache line at the present virtual
index before taking an exception.
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