Mips Technologies R4000 - Cache Error (Cacheerr) Register (27)

Chapter 5
116 MIPS R4000 Microprocessor User's Manual
Cache Error (CacheErr) Register (27)
The 32-bit read-only CacheErr register processes ECC errors in the
secondary cache and parity errors in the primary cache. Parity errors
cannot be corrected.
All single- and double-bit ECC errors in the secondary cache tag and data
are detected; single-bit errors in the cache tag are automatically corrected.
Single-bit ECC errors in the secondary cache data are not automatically
corrected.
The CacheErr register holds cache index and status bits that indicate the
source and nature of the error; it is loaded when a Cache Error exception
is asserted.
Figure 5-12 shows the format of the CacheErr register and Table 5-10
describes the CacheErr register fields.
Figure 5-12 CacheErr Register Format
Table 5-10 CacheErr Register Fields
Field Description
ER
Type of reference
0 → instruction
1 → data
EC
Cache level of the error
0 → primary
1 → secondary
ED
Indicates if a data field error occurred
0 → no error
1 → error
ET
Indicates if a tag field error occurred
0 → no error
1 → error
CacheErr Register
31
EI
19
20
ER
ES
1
30 28 25
1
24
23 22 21
0
11
SIdx
3
PIDx
EBEE
111
ETEDEC
11
262729
1
EW