Mips Technologies R4000 - Sra Shift Right Arithmetic

Appendix A
A-146 MIPS R4000 Microprocessor User's Manual
Format:
SRA rd, rt, sa
Description:
The contents of general register rt are shifted right by sa bits, sign-
extending the high-order bits.
The result is placed in register rd.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
Exceptions:
None
SRA
Shift Right Arithmetic
31 2526 2021 1516
SPECIAL 0 rt
655
rd sa SRA
55 6
11 10 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
SRA
32 T: GPR[rd] ← (GPR[rt]
31
)
sa
|| GPR[rt]
31...sa
64 T: s ← 0 || sa
temp ← (GPR[rt]
31
)
s
|| GPR[rt]
31...s
GPR[rd] ← (temp
31
)
32
|| temp