Mips Technologies R4000 - Cache Error Exception

Chapter 5
132 MIPS R4000 Microprocessor User's Manual
Cache Error Exception
Cause
The Cache Error exception occurs when either a secondary cache ECC
error, primary cache parity error, or SysAD bus parity/ECC error
condition occurs and error detection is enabled. This exception is not
maskable, but error detection can be disabled if either ERL or DE = 1 in the
Status register.
Processing
The processor sets the ERL bit in the Status register, saves the exception
restart address in the ErrorEPC register, records information about the
error in the CacheErr register, and then transfers to a special vector that is
always in uncached space (Tables 5-11 and 5-12). No other registers are
changed. Cache Error exception processing is shown in Figure 5-15.
Servicing
Unlike other exception conditions, cache errors cannot be avoided while
operating at exception level, so Cache Error exceptions must be handled
from exception level. Any general register used by the handler must be
saved before use and restored before return; this includes the registers
available to regular exception handlers without save/restore. When
ERL=1 in the Status register, the user address region becomes a 2
31
-byte
uncached space mapped directly to physical addresses, allowing the
Cache Error handler to save registers to memory without using a register
to construct the address. The handler can save and restore registers using
operating system-reserved locations in low physical memory by using R0
as the base register for load and store instructions. All errors should be
logged. To correct single-bit ECC errors in the secondary cache, the
system uses the CACHE instruction. Execution then resumes through an
ERET instruction. To correct cache parity errors and non-single-bit ECC
errors in unmodified cache blocks, the system uses the CACHE instruction
to invalidate the cache block, overwrites the old data through a cache miss,
and resumes execution with an ERET. Other errors are not correctable and
are likely to be fatal to the current process. The exception handler cannot
be interrupted by another Cache Error exception because error detection
is disabled while ERL = 1, so the handler should avoid actions which
might cause an unnoticed cache error. The R4400 (but not R4000)
implements the EW bit in the CacheErr register to record a nonrecoverable
error occurring while ERL = 1.