Mips Technologies R4000 - Bus Error Exception

Chapter 5
134 MIPS R4000 Microprocessor User's Manual
Bus Error Exception
Cause
A Bus Error exception is raised by board-level circuitry for events such as
bus time-out, backplane bus parity errors, and invalid physical memory
addresses or access types. This exception is not maskable.
A Bus Error exception occurs either when the SysCmd(5) bit indicates the
data is erroneous (see Chapter 12) or the IvdErr* signal is asserted
(Chapter 12). This can only occur when a cache miss refill, uncached
reference, or an unbuffered write occurs synchronously; a Bus Error
exception resulting from a buffered write transaction must be reported
using the general interrupt mechanism.
Processing
The common interrupt vector is used for a Bus Error exception. The IBE
or DBE code in the ExcCode field of the Cause register is set, signifying
whether the instruction (as indicated by the EPC register and BD bit in the
Cause register) caused the exception by an instruction reference, load
operation, or store operation.
The EPC register contains the address of the instruction that caused the
exception, unless it is in a branch delay slot, in which case the EPC register
contains the address of the preceding branch instruction and the BD bit of
the Cause register is set. Bus Error processing is shown in Figure 5-17.
Servicing
The physical address at which the fault occurred can be computed from
information available in the CP0 registers.
• If the IBE code in the Cause register is set (indicating an
instruction fetch reference), the virtual address is contained in
the EPC register.
• If the DBE code is set (indicating a load or store reference), the
instruction that caused the exception is located at the virtual
address contained in the EPC register (or 4+ the contents of the
EPC register if the BD bit of the Cause register is set).
The virtual address of the load and store reference can then be obtained by
interpreting the instruction. The physical address can be obtained by
using the TLBP instruction and reading the EntryLo register to compute