Chapter 11
278 MIPS R4000 Microprocessor User's Manual
Load
A shown in Figure 11-12, when a processor misses in the primary and
secondary caches on a load, the processor issues a read request. The
subsystem external agent translates this to a read request on the bus. The
returned data is loaded in either the clean exclusive or shared state, based
on the shared indication returned with the read response data.
†
Store
In this system model, when a processor misses in the primary and
secondary caches on a store, it issues a read request with exclusivity; this
is translated to a read exclusive on the bus and data is loaded in the dirty
exclusive state.
When a processor hits in the cache on a store to shared data, it issues an
invalidate request that must be forwarded to the system bus. Before the
store can be completed and the state changed to dirty exclusive, the
invalidate request must be acknowledged.
Processor Coherent Read Request and Read Response
In this system model, when one of the external agents observes a coherent
read request on the system bus, it does not take immediate action. Instead,
the external agent issues an intervention request to its processor during
the read response. This is referred to as a response complete read protocol;
that is, the read is complete after the read response has occurred.
At the end of the read response, each of the external agents in the system
model indicate whether it was able to obtain the state of the cache line that
is the target of the intervention; if successful, the external agent indicates
either sharing or takeover. Takeover occurs when an external agent
discovers that its processor has a dirty exclusive copy of the cache line that
is the target of the read.
The read response is extended until all external agents have obtained the
state of the cache line from their processors.
In this system model, the response from an external agent at the end of a
read response depends on whether the read request was an ordinary read
request or a read exclusive request. These are described in the following
sections.
† The shared indication is the result of an intervention request to another processor, and is
supplied by an external agent that is a part of the other three processor subsystems.
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