Chapter 11
276 MIPS R4000 Microprocessor User's Manual
System Model
To describe the implications of a coherency conflict, this section uses a
system model that is snooping, split-read, and bus-based; I/O is not
considered in this model.
The system model used in this example has the following components:
• Four processor subsystems, each consisting of an R4000MC
processor, a secondary cache, and an external agent (shown in
Figure 11-12). The external agent communicates with the
R4000MC processor, accepting processor requests and issuing
external requests. Likewise, the system bus issues and receives
bus requests.
• A memory subsystem that communicates with main memory
and the system bus.
• A system bus that has the following characteristics:
- It is a multiple master, request-based, arbitrated bus.
When an agent wishes to perform a transaction on the
bus, it must request the bus and wait for global
arbitration logic to assert a grant signal before assuming
mastership of the bus. Once mastership has been
granted, the agent can begin a transaction.
- It supports read transactions, read exclusive transactions,
write transactions, and invalidate transactions.
- It is a split-read bus. This means bus operations can
separate a read request from the return of its data.
- It is a snooping bus. All agents connected to the bus
must monitor all bus traffic to correctly maintain cache
coherency.
• All of the TLB pages in the system have either a noncoherent or
a sharable coherency attribute. (Noncoherent data is not
allowed; noncoherent page attributes are used for instructions
only.)
• The sharable coherency attribute allows data to be shared
between the four caches in the system by using a write
invalidate cache coherency protocol.
• The secondary cache states used are invalid, shared, clean
exclusive, and dirty exclusive; the dirty shared secondary
cache state is not allowed.
To Next Page
Loading...