Chapter 7
188 MIPS R4000 Microprocessor User's Manual
7.1 Exception Types
The FP Control/Status register described in Chapter 6 contains an Enable bit
for each exception type; exception Enable bits determine whether an
exception will cause the FPU to initiate a trap or set a status flag.
• If a trap is taken, the FPU remains in the state found at the
beginning of the operation and a software exception handling
routine executes.
• If no trap is taken, an appropriate value is written into the FPU
destination register and execution continues.
The FPU supports the five IEEE Standard 754 exceptions:
• Inexact (I)
• Underflow (U)
• Overflow (O)
• Division by Zero (Z)
• Invalid Operation (V)
Cause bits, Enables, and Flag bits (status flags) are used.
The FPU adds a sixth exception type, Unimplemented Operation (E), to
use when the FPU cannot implement the standard MIPS floating-point
architecture, including cases in which the FPU cannot determine the
correct exception behavior. This exception indicates the use of a software
implementation. The Unimplemented Operation exception has no Enable
or Flag bit; whenever this exception occurs, an unimplemented exception
trap is taken (if the FPU interrupt input to the CPU is enabled).
Figure 7-1 illustrates the Control/Status register bits that support
exceptions.
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