Mips Technologies R4000 - Notes on a Secondary Cache Write Cycle

MIPS R4000 Microprocessor User's Manual 387
Secondary Cache Interface
Figure 13-5 Timing Diagram of an 8-Word Write Cycle
Notes on a Secondary Cache Write Cycle
When receiving data from the System interface, the first data doubleword
can arrive several cycles before the second data doubleword. In this case,
the cache state machine enters a wait-state that extends SCWR* until
t
WrSUp
period after the second data item is transmitted.
SCWR*
t
Wr1Dly
t
Wr2Dly
t
WrRc
SCOE*
SCDCS*
SCTCS*
t
WrSUp
t
WrSUp
PCycle
1 2 3 4 5 6 7 8
SCAddr(17:1)
Address
SCAddr(0)
First_Address Second_Address
SCData(63:0)/
First_Data Second_Data
SCTag(24:0)/
First_Data Second_Data
SCData(127:64)
First_Data Second_Data
t
WrRc
SCTChk(6:0)
SCDChk(7:0)
First_Data_MS/DTag_Chk
SCDChk(15:8)
Second_Data_MS/DTag_Chk
SCAPar(2:0)