MIPS R4000 Microprocessor User's Manual 377
System Interface
Table 12-27 Coherent Data Identifiers Encoding of SysCmd(2:0)
12.10 System Interface Addresses
System interface addresses are full 36-bit physical addresses presented on
the least-significant 36 bits (bits 35 through 0) of the SysAD bus during
address cycles; the remaining bits of the SysAD bus are unused during
address cycles.
Addressing Conventions
Addresses associated with doubleword, partial doubleword, word, or
partial word transactions and update requests, are aligned for the size of
the data element. The system uses the following address conventions:
• Addresses associated with block requests are aligned to
double-word boundaries; that is, the low-order 3 bits of
address are 0.
• Doubleword requests set the low-order 3 bits of address to 0.
• Word requests set the low-order 2 bits of address to 0.
• Halfword requests set the low-order bit of address to 0.
• Byte, tribyte, quintibyte, sextibyte, and septibyte requests use
the byte address.
†This state also occurs if the line does not exist in the cache.
SysCmd(2:0) Cache State
0 Invalid
†
1 Reserved
2 Reserved
3 Reserved
4 Clean Exclusive
5 Dirty Exclusive
6 Shared
7 Dirty Shared
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