MIPS R4000 Microprocessor User's Manual 161
Floating-Point Unit
IEEE Standard 754
IEEE Standard 754 specifies that floating-point operations detect certain
exceptional cases, raise flags, and can invoke an exception handler when
an exception occurs. These features are implemented in the MIPS
architecture with the Cause, Enable, and Flag fields of the Control/Status
register. The Flag bits implement IEEE 754 exception status flags, and the
Cause and Enable bits implement exception handling.
Control/Status Register FS Bit
When the FS bit is set, denormalized results are flushed to 0 instead of
causing an unimplemented operation exception.
Control/Status Register Condition Bit
When a floating-point Compare operation takes place, the result is stored
at bit 23, the Condition bit, to save or restore the state of the condition line.
The C bit is set to 1 if the condition is true; the bit is cleared to 0 if the
condition is false. Bit 23 is affected only by compare and Move Control To
FPU instructions.
Control/Status Register Cause, Flag, and Enable Fields
Figure 6-5 illustrates the Cause, Flag, and Enable fields of the Control/Status
register.
Cause Bits
Bits 17:12 in the Control/Status register contain Cause bits, as shown in
Figure 6-5, which reflect the results of the most recently executed
instruction. The Cause bits are a logical extension of the CP0 Cause register;
they identify the exceptions raised by the last floating-point operation and
raise an interrupt or exception if the corresponding enable bit is set. If
more than one exception occurs on a single instruction, each appropriate
bit is set.
The Cause bits are written by each floating-point operation (but not by
load, store, or move operations). The Unimplemented Operation (E) bit is
set to a 1 if software emulation is required, otherwise it remains 0. The
other bits are set to 0 or 1 to indicate the occurrence or non-occurrence
(respectively) of an IEEE 754 exception.
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