Appendix D
D-2 MIPS R4000 Microprocessor User's Manual
For situations where the jitter associated with the operation of the ∆i/∆t
control mechanism cannot be tolerated and where the variation in
temperature and supply voltage after ColdReset* is expected to be small,
the ∆i/∆t control mechanism can be instructed to lock during ColdReset*
and thereafter retain its control values. The EnblDPLLR mode bit is set
and EnblDPLL is cleared for this mode of operation.
In addition, if both the EnblDPLL and EnblDPLLR mode bits are cleared,
the speed of the output buffers are set by the InitP(3:0) and InitN(3:0)
mode bits.
D.2 Delay Times
Currently, delays of 0.5T, 0.75T, and T are supported, corresponding to the
Drv0_50, Drv0_75, and Drv1_00 mode bits, where T is the MasterClock
period. For example, in Drv0_75 mode, the entire signal transmission path
including the clock-to-Q, output buffer drive time, board flight time, input
buffer delay, and setup time will be traversed in 0.75 * the MasterClock
period, plus or minus the jitter due to the ∆i/∆t control mechanism.
All output drivers on the R4000, with the exception of the clock drivers, are
controlled by the ∆i/∆t control mechanism. The delay due to the output
buffer drive time component of the SCAddr(17:0), SCOEB, SCWRB,
SCDCSB, and SCTCSB pins is approximately 66% of the delay of drivers
of the other pins.
By measuring the transmission line delay of the trace that connects the
R4000 IO_Out and IO_In pins, the R4000 determines the worst case
propagation delay from an R4000 output driver to a receiving device. This
representative trace must have one and a half times the length and
approximately the same capacitive loading as the worst case trace on any
R4000 output.
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