Chapter 7
192 MIPS R4000 Microprocessor User's Manual
7.4 FPU Exceptions
The following sections describe the conditions that cause the FPU to
generate each of its exceptions, and details the FPU response to each
exception-causing condition.
Inexact Exception (I)
The FPU generates the Inexact exception if one of the following occurs:
• the rounded result of an operation is not exact, or
• the rounded result of an operation overflows, or
• the rounded result of an operation underflows and both the
Underflow and Inexact Enable bits are not set and the FS bit is
set.
The FPU usually examines the operands of floating-point operations
before execution actually begins, to determine (based on the exponent
values of the operands) if the operation can possibly cause an exception. If
there is a possibility of an instruction causing an exception trap, the FPU
uses a coprocessor stall to execute the instruction.
It is impossible, however, for the FPU to predetermine if an instruction will
produce an inexact result. If Inexact exception traps are enabled, the FPU
uses the coprocessor stall mechanism to execute all floating-point
operations that require more than one cycle. Since this mode of execution
can impact performance, Inexact exception traps should be enabled only
when necessary.
Trap Enabled Results: If Inexact exception traps are enabled, the result
register is not modified and the source registers are preserved.
Trap Disabled Results: The rounded or overflowed result is delivered to
the destination register if no other software trap occurs.
To Next Page
Loading...