Mips Technologies R4000 - System Interface Signals

MIPS R4000 Microprocessor User's Manual 201
R4000 Processor Signal Descriptions
8.1 System Interface Signals
System interface signals provide the connection between the R4000
processor and the other components in the system. IvdAck* and IvdErr*
signals are applicable only on R4000MC; on the R4000SC they must be tied
to Vcc. The remaining signals are available on all three of the package
configurations.
Table 8-1 lists the system interface signals.
Table 8-1 System Interface Signals
Name Definition Direction Description
ExtRqst* External request Input
An external agent asserts ExtRqst*to
request use of the System interface. The
processor grants the request by asserting
Release*.
IvdAck*
Invalidate
acknowledge
Input
An external agent asserts IvdAck*to
signal successful completion of a
processor invalidate or update request
(R4000MC only; tie to Vcc on R4000SC).
IvdErr* Invalidate error Input
An external agent asserts IvdErr*to
signal unsuccessful completion of a
processor invalidate or update request
(R4000MC only; tie to Vcc on R4000SC).
Release* Release interface Output
In response to the assertion of ExtRqst*,
the processor asserts Release*, signalling
to the requesting device that the System
interface is available.
RdRdy* Read ready Input
The external agent asserts RdRdy*to
indicate that it can accept processor read,
invalidate, or update requests in both
secondary-cache and no-secondary-cache
mode; or can accept a read followed by
write request, a read followed by a
potential update request, or a read
followed by a potential update followed
by a write request in secondary cache
mode.
SysAD(63:0)
System address/
data bus
Input/
Output
A 64-bit address and data bus for
communication between the processor
and an external agent.