Mips Technologies R4000 - Page 230

Chapter 8
200 MIPS R4000 Microprocessor User's Manual
Figure 8-1 R4000 Processor Signals
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
ValidIn*
ValidOut*
ExtRqst*
Release*
WrRdy*
IvdAck*
(3)
IvdErr*
(3)
TClock(1:0)
RClock(1:0)
MasterClock
MasterOut
SyncOut
SyncIn
IOOut
IOIn
VCCOk
ColdReset*
Reset*
Fault*
VccP
VssP
Status(7:0)
(4)
VccSense
(1)
VssSense
(1)
SCData (127:0)
SCDChk (15:0)
SCTag (24:0)
SCTChk (6:0)
SCAddr (17:1)
SCAddr0 (w,x,y,z)
SCAPar(2:0)
SCWr(w,x,y,z)*
SCDCS*
SCTCS*
Int(5:1)*
(2)
Int0*
NMI*
ModeClock
ModeIN
JTDI
JTDO
JTMS
JTCK
(1) = R4000SC and R4000MC only (2) = R4000PC only
SCOE*
Initialization
Interface
Secondary Cache Interface (1)Interrupt Interface
System InterfaceClock/Control Interface
R4000
Logic
Symbol
64
8
9
2
2
8
128
16
25
7
17
4
3
4
5
RdRdy*
(3) = R4000MC only
JTAG
Interface
(4) = R4400 only