Chapter 11
248 MIPS R4000 Microprocessor User's Manual
Secondary Cache Size
Table 11-2 lists the range of secondary cache sizes. The secondary cache is
user-configurable at boot time through the boot-mode bits (see Chapter 9);
it can be a joint cache, containing both data and instructions in a single
cache, or split into separate data and instruction caches.
Table 11-2 Secondary Cache Sizes
Variable-Length Cache Lines
A cache line is the smallest unit of information that can be fetched from the
cache, and that is represented by a single tag.
†
A primary cache line can
be either 4 or 8 words in length; a secondary cache line can be either 4, 8,
16, or 32 words in length. Primary cache line length is set in the Config
register; see Chapter 4 for more information. Secondary cache line length
is set at boot time through the boot-mode bits, as described in Chapter 9.
Upon a cache miss in both primary and secondary caches, the missing
secondary cache line is loaded first from memory into the secondary
cache, whereupon the appropriate subset of the secondary cache line is
loaded into the primary cache.
The primary cache line length can never be longer than that of the
secondary cache; it must always be less than or equal to the secondary
cache line length. This means the secondary cache cannot have a 4-word
line length while the primary cache has an 8-word line length.
Cache Organization and Accessibility
This section describes the organization of the primary and secondary
caches, including the manner in which they are mapped, the addressing
(either virtual or physical) used to index the cache, and composition of the
cache lines. The primary instruction and data caches are indexed with a
virtual address (VA), while the secondary cache is indexed with a physical
address (PA).
† Primary and secondary cache tags are described in the following sections.
Cache Minimum Size Maximum Size
Secondary Joint Cache 128 Kbytes 4 Mbytes
Secondary Split I-Cache 128 Kbytes 2 Mbytes
Secondary Split D-Cache 128 Kbytes 2 Mbytes
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