MIPS R4000 Microprocessor User's Manual 129
CPU Exception Processing
TLB Refill Exception
Cause
The TLB refill exception occurs when there is no TLB entry to match a
reference to a mapped address space. This exception is not maskable.
Processing
There are two special exception vectors for this exception; one for
references to 32-bit address spaces, and one for references to 64-bit address
spaces. The UX, SX, and KX bits of the Status register determine whether
the user, supervisor or kernel address spaces referenced are 32-bit or 64-
bit spaces. All references use these vectors when the EXL bit is set to 0 in
the Status register. This exception sets the TLBL or TLBS code in the
ExcCode field of the Cause register. This code indicates whether the
instruction, as shown by the EPC register and the BD bit in the Cause
register, caused the miss by an instruction reference, load operation, or
store operation.
When this exception occurs, the BadVAddr, Context, XContext and EntryHi
registers hold the virtual address that failed address translation. The
EntryHi register also contains the ASID from which the translation fault
occurred. The Random register normally contains a valid location in which
to place the replacement TLB entry. The contents of the EntryLo register
are undefined. The EPC register contains the address of the instruction
that caused the exception, unless this instruction is in a branch delay slot,
in which case the EPC register contains the address of the preceding
branch instruction and the BD bit of the Cause register is set.
TLB Refill exception processing is shown in Figure 5-17.
Servicing
To service this exception, the contents of the Context or XContext register
are used as a virtual address to fetch memory locations containing the
physical page frame and access control bits for a pair of TLB entries. The
two entries are placed into the EntryLo0/EntryLo1 register; the EntryHi and
EntryLo registers are written into the TLB.
It is possible that the virtual address used to obtain the physical address
and access control information is on a page that is not resident in the TLB.
This condition is processed by allowing a TLB refill exception in the TLB
refill handler. This second exception goes to the common exception vector
because the EXL bit of the Status register is set.
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