Mips Technologies R4000 - Accessing a Split Secondary Cache; Scdchk Bus; SCTAG Bus

MIPS R4000 Microprocessor User's Manual 381
Secondary Cache Interface
13.3 Accessing a Split Secondary Cache
When the secondary cache is split into separate instruction and data
portions, assertion of the high-order SCAddr bit, SCAddr(17), enables the
instruction half of the cache.
It is possible to design a cache that supports both joint and split
instruction/data configurations of less than the maximum cache size; in
doing so, SCAddr(12:0) must address the cache in all configurations.
SCAddr(17) must support the split instruction/data configuration, and
any of SCAddr(16:14) bits can be omitted, because of the fixed width of the
physical tag array.
13.4 SCDChk Bus
The secondary cache data check bus, SCDChk, is divided into two fields
to cover the upper and lower 64 bits of SCData. This form is required by
the 64-bit width of internal data paths.
13.5 SCTAG Bus
The secondary cache tag bus, SCTag, is divided into three fields, as shown
in Figure 13-1. The CS field indicates the cache state: invalid, clean
exclusive, dirty exclusive, shared, or dirty shared. The PIdx field is an
index to the virtual address of primary cache lines that can contain data
from the secondary cache. Bits 18:0 contain the upper physical address.
Figure 13-1 SCTag Fields
TheSCDCS* and SCTCS* signals disable reads or writes of either the data
array or tag array when the opposite array is being accessed. These signals
are useful for saving power on snoop and invalidate requests since access
to the data array is not necessary. These signals also write data from the
primary data cache to the secondary cache.
Physical_TagCS PIdx
3
3
19
24 22 21 19 18
0