Mips Technologies R4000 - Connecting to a CMOS Logic System

Chapter 10
238 MIPS R4000 Microprocessor User's Manual
Connecting to a CMOS Logic System
The processor uses matched delay clock buffers to generate aligned clocks
to external CMOS logic. A matched delay clock buffer is inserted in the
SyncOut/SyncIn alignment path of the processor, skewing SyncOut,
MasterOut, RClock, and TClock to lead MasterClock by the buffer delay
amount, while leaving PClock aligned with MasterClock.
The remaining matched delay clock buffers are available to generate a
buffered version of TClock aligned with MasterClock. Alignment error
of this buffered TClock is the sum of the maximum delay mismatch of the
matched delay clock buffers, and the maximum clock jitter of TClock.
As the global system clock for the discrete logic that forms the external
agent, the buffered version of TClock clocks registers that sample
processor outputs, as well as clocking the registers that drive the processor
inputs.
The transmission time for a signal from the processor to an external agent
composed of discrete CMOS logic devices can be calculated from the
following equation:
Transmission Time = (TClock period) – (t
DO
for R4000)
– (External Sample Register Setup Time)
– (Maximum External Clock Buffer Delay Mismatch)
– (Maximum Clock Jitter for R4000 Internal Clocks)
– (Maximum Clock Jitter for TClock)
Figure 10-7 is a block diagram of a system without phase lock, employing
the R4000 processor and an external agent composed of both a gate array
and discrete CMOS logic devices.